concept and advantages of Transient and Non-Transient memory in ARM? -

in arm architecture manual mentioned cache can transient , non transient , implementation defined. failing understand concept , use of transient memory respect cache. trying write software enabling mmu , have enabled l1 , l2 cache. using lpae. know mair register controls attribute. failing documentation it.

i want know concept want check feasibility of applying present design.

arm-v7-a-r page 134

"for armv7-a implementation includes large physical address extension, implementation defined whether transient attribute supported cacheable normal memory regions. if implementation supports attribute, set of possible cacheability attributes normal memory region becomes:
• write-through cacheable, non-transient
• write-back cacheable, non-transient
• write-through cacheable, transient
• write-back cacheable, transient
• non-cacheable."

the arm arm says, shortly after part you've quoted:

the transient attribute indicates benefit of caching relatively short period, , therefore might better restrict allocation, avoid possibly casting-out other, less transient, entries.

in other words, it's hint cache system. as peter suggests in comments, when cache has predictable replacement policy (e.g. lru or round-robin) implemented allocating straight positions close eviction. alternative transient/non-temporal accesses allocate lower levels of cache, typically represent less used data whatever's hot in l1.

that has theoretical benefit streaming-type workloads - example, mapping large data buffers cacheable transient, processing algorithm working through buffers still benefit cache in terms of access locality (i.e. multiple hits in same line) , automatic prefetching of subsequent lines regular access patterns, without thrashing , disrupting instruction fetches, stack accesses, etc. in rest of cache. on other hand, though, modern caches clever enough @ least detect sustained regular access patterns of writes , automatically enter non-allocating streaming mode, gives of same benefit transparently without needing programmer muck attributes.

from practical perspective, important concern whether it's worth worrying @ all: in general, isn't. having had quick through trms, cortex-a7 ignores transient attribute entirely; cortex-a15 might go wrong if try use it; cortex-a12/17 , marvell's v7 core (per public armada xp functional spec) don't seem mention @ all, in absence of specific implementation-specific definition i'd guess may ignore (particularly since mention pseudo-random cache replacement policies). i've no idea qualcomm krait or other implementations, public documentation isn't forthcoming.

from little know cpu design, transient attribute has impression of being 1 of features not offers no benefit outside particular niche, adds comparatively large cost design , verification. in other words, doubt anyone's going there without specific requirement, although fact exists in architecture @ means there's some hardware out there running some workload better off implementing it. unless know have hardware , workload, though, i'd inclined forget it.