assembly - ARM GIC v3 configuration to use GICR_ registers -

i trying configure timer interrupt kite processor on fast model.

i have enabled gicd enable timer interrupt , updating pending once timer 0 receive cpu interface need enable in gicr. when trying enable in gicr, registers not getting updated when run simulation. updates gicr_igroupr0 register gicr_isenabler0 register not getting updated.

does have idea why 1 register able update , not others?

do need specific configuration use gicr registers? why 1 register able update?

code:

#define gicc_offset 0x00 #define gicd_offset 0x00 #define gicr_offset 0x0100000 #define gicr_sgi_ppi_offset 0x110000 // core 0 /* cbar read , offset distributor , cpu interfaces           added */ #define gicreg(gic, reg) (*reg32(hal_arm_gic_get_base() + (reg)))  /* redistributor control registor gicr_ */  #define gicr_ctlr (gicr_offset + 0x00)  /* redistributor sgi , ppi core 0*/ #define gicr_igroupr0 (gicr_sgi_ppi_offset + 0x80) #define gicr_isenabler0 (gicr_sgi_ppi_offset + 0x100) #define gicr_icenabler0 (gicr_sgi_ppi_offset + 0x180) #define gicr_ispendr0 (gicr_sgi_ppi_offset + 0x200) #define gicr_icpendr0 (gicr_sgi_ppi_offset + 0x280) #define gicr_isactiver0 (gicr_sgi_ppi_offset + 0x300) #define gicr_icactiver0 (gicr_sgi_ppi_offset + 0x380) #define gicr_ipriorityr(n) (gicr_sgi_ppi_offset + 0x400 + (n) * 4) #define gicr_icfgr0 (gicr_sgi_ppi_offset + 0xc00) #define gicr_icfgr1 (gicr_sgi_ppi_offset + 0xc04)  /* distribution regs */ #define gicd_ctlr               (gicd_offset + 0x000u) #define gicd_typer              (gicd_offset + 0x004u) #define gicd_iidr               (gicd_offset + 0x008u) #define gicd_igroupr(n)         (gicd_offset + 0x080u + (n) * 4u) #define gicd_isenabler(n)       (gicd_offset + 0x100u + (n) * 4u) #define gicd_icenabler(n)       (gicd_offset + 0x180u + (n) * 4u) #define gicd_ispendr(n)         (gicd_offset + 0x200u + (n) * 4u) #define gicd_icpendr(n)         (gicd_offset + 0x280u + (n) * 4u) #define gicd_isactiver(n)       (gicd_offset + 0x300u + (n) * 4u) #define gicd_icactiver(n)       (gicd_offset + 0x380u + (n) * 4u) #define gicd_ipriorityr(n)      (gicd_offset + 0x420u + (n) * 4u) #define gicd_itargetsr(n)       (gicd_offset + 0x800u + (n) * 4u) #define gicd_icfgr(n)           (gicd_offset + 0xc00u + (n) * 4u) 

gic v3 configuration:

// check whether gicv3 system registers available mrc p15, 0, r7, c0, c1, 1   @ id_pfr1 ubfx    r7, r7, #28, #4 cmp r7, #1 bne 2f  // enable system register accesses mrc p15, 4, r7, c12, c9, 5  @ icc_hsre orr r7, r7, #( (1 << 0) | (1 << 3)) mcr p15, 4, r7, c12, c9, 5  @ icc_hsre isb  // sre bit forced 0 firmware. // check whether sticks before accessing other sysreg mrc p15, 4, r7, c12, c9, 5  @ icc_hsre tst r7, #icc_sre_el2_sre beq 2f mov r7, #0 mcr p15, 4, r7, c12, c11, 0 @ ich_hcr 2: mov r0, #0x1 mrc p15, 0, r0, c12, c12, 6 orr r0, r0, #0x1 mcr p15, 0, r0, c12, c12, 6 // group 0 enable mrc p15, 0, r0, c12, c12, 7 orr r0, r0, #0x1 mcr p15, 0, r0, c12, c12, 7 // group 1 enable 

after days of search , tries, found issue in arm kite processor itself. arm has released untested start development partner companies.

sad hear this.